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XE1203F
The Frequency Synthesizer generates the local oscillator (LO) signal for the receiver section as well as the
continuous phase FSK (CPFSK) modulated signal for the transmitter section. The core of the synthesizer is
implemented with a Sigma-Delta PLL architecture. The frequency is programmable with a minimum step-size of
500 Hz in the 433, 868 and 915 MHz frequency bands. This block includes a crystal oscillator which provides the
frequency reference for the PLL. This reference frequency can also be used as a reference clock for the external
microcontroller on the CLKOUT pin.
4.3.1 Clock Output for external processor
A reference clock can be generated by XE1203F for use by an external microcontroller. The RTParam_Clkout
configuration bit determines the status of the CLKOUT pin. When set high CLKOUT is enabled, otherwise it’s
disabled. The output frequency at CLKOUT is defined by the value of the ADParam_Clkfreq parameter. The output
frequency at CLKOUT is the reference oscillator frequency divided by 4, 8, 16 or 32. With the reference oscillator
frequency at 39 MHz this provides a reference clock at 9.75 MHz, 4.87 MHz, 2.44 MHz or 1.22 MHz, respectively.
This clock signal is disabled in Sleep Mode.
? Semtech 2008
17
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